1. Field of the Invention
This invention relates to the field of processors for data-processing systems, and in particular to a processor having a variable length pipeline for executing multiple instruction sets.
2. Description of the Related Art
In a data-processing system the basic logical arithmetic computational operations are performed by the processor. For this purpose there is provided within the processor a number of registers and logic circuits. The processor registers are used to receive, hold, and transmit information (data and instructions) used by the processor. Several different types of registers are provided within the typical processor. For example, an accumulator register temporarily stores data and accumulates the results of logical or arithmetic operations. A program counter stores the address of the next instruction in memory to be executed. An instruction register stores the instruction code (also known as the operation code) portion of instruction which is currently being executed by the processor, and an address register or data counter stores the operand portion of the currently executing instruction. Throughout the specification the term "instruction" will hereafter be used to refer specifically to the instruction code or operation code portion of an instruction.
To enable the processor to perform all of the intended arithmetic and logical operations which are desired to be performed, the processor is provided with the capability of executing a repertory of individual instructions collectively known as an instruction set. Individual instructions are executed by the processor to perform such operations as loading information into a register, transferring information between registers or between registers and memory, comparing the contents of two registers, and so forth. Such instructions may be thought of as "macroinstructions" since the execution of one such instruction by the processor comprises a number of sub-operations or "microinstructions" by the circuitry making up the instruction execution control logic portion of the processor. During the execution of a single instruction many different logic gates in the instruction execution control logic circuitry may be opened and closed in a precise sequence in order to implement the particular macro-operation called for by the instruction. The opening or closing of each gate may be individually viewed as a single microinstruction.
The instruction format convergence or compatibility problem is fairly well known. Several general strategies have evolved for dealing with this compatibility problem. One purely software solution involves writing programs in high-level language for compilation specifically for the machine which is to run the program. Thus, programs must be re-compiled into machine language code for each new machine required to run them. A library of tested programs or algorithms can be built up over time and can be migrated to new machines by re-compiling them. This approach necessarily involves the use of a compiler or translator which, of course, must be written for each new machine. This is a substantial effort in most instances, and in the end does not permit incompatible instruction formats to reside in the same machine because the instructions compiled for given machine are compatible with, and are in the format of, that specific machine alone.
It is very useful for a processor to have the capability of executing an instruction set for a different computer in addition to its own instruction set. Normally the processor is endowed with a unique instruction set comprising a plurality of individual operation code words, each of which comprises a distinctive combination of ones and zeros, in response to which the instruction decoding circuitry and instruction execution control circuitry perform all of the individual microinstructions necessary to carry out the particular instruction. A known emulation technique, referred to as microprogramming, allows a processor to execute instruction sets from several different computers. For example, several known computer systems utilized a special program called a "microprogram" to execute a plurality of individual microinstructions which together comprise a basic macroinstruction. In response to a given macroinstruction, a special processor memory known as a control store is accessed and a micro-program corresponding to the macroinstruction is executed, with each of the individual microinstructions, serving to control the desired operation of the instruction execution control logic circuitry. This approach involves the use of advanced assemblers to produce the instruction decode tables that are to be written in the variable decode logic.
While the technique of micro-programming has been utilized in a number of mainframe and minicomputer systems, it does not lend itself well to microcomputer systems, where the space necessary for a control store is difficult to justify on the limited silicon area of a large-scale integrated (LSI) circuit device. There is therefore a need for a mechanism in a processor permitting the processor to execute two or more instruction sets without requiring the expensive consumption of silicon space in an LSI circuit device.
A variant on the micro-programming approach to resolving the compatibility problem involves reservation of a bit or some bit combination in the instruction format for the machine that is to run the program. The extra bit or bit combinations are utilized to flag instructions which are non-native format for the machine. Whenever such a flag combination is encountered, the instruction containing it can be decoded using different rules from the native instruction decode rules. This scheme allows non-native instructions to be located anywhere in the instruction store, but does so at the expense and inconvenience of lengthening the native instruction word by adding the additional bit or bit combinations. This has the effect of using up available instruction decode permutations that might otherwise be used for more beneficial purposes within the machine.
It will be appreciated that the capability of a processor to emulate another processor by executing the instruction set of the other processor adds a great deal of flexibility and versatility to a computer system, which can result ultimately in substantial savings to the user of such system.